RZ/T1 Development Kit / Board

The main CPU core of the RZ/T1 is a 32-bit ARM Cortex®-R4F. This allows the acceleration of hard real-time control. Further performance enhancement can be realised by use of the R-IN Engine which supports HW-RTOS acceleration, which allows cutting-edge speeds for task switching and interrupt response. Options are available with an integrated encoder interface.

The family is designed to give a compatible upgrade path to existing Renesas SuperH and RX solutions, as the main peripherals and sub-modules (e.g. timers) are backwards compatible. Additionally the dedicated encoder can be directly triggered by the motor control timer unit allowing for a faster response and lower CPU load.

The family supports connection to the Ethernet network via MII or RMII or EtherCAT slave interface enabling the implementation of several Industrial Ethernet protocols such as EtherCAT, all on the same device.

Main Features:

  • High-performance ARM Cortex® R4F CPU core 600 MHz max. clock frequency
    • Harvard architecture with 8-stage pipeline
    • I/D 8 KB / 8 KB L1 cache memory
    • A/B TCM 512 KB / 32 KB memory
    • 0 KB / 1 MB shared memory with ECC
  • R-IN Engine 150 MHz max. clock frequency
  • EtherCAT slave support
  • Encoder interface 
  • Double Floating Point Unit compliant with IEE754 
  • Vectored interrupt controller (VIC) 
  • Hardware Real-time OS Accelerator 
  • Ethernet Accelerator 
  • Integrated 2-port Gigabit Ethernet Switch 
  • Safety control (ECC RAM support, CRC (32-bit), clock monitor, independent WDT) 
  • Secure boot (optional)
  • 2 12-bit ADC, 4 ΔΣ I/F interface 
  • 1ch QSPI Flash interface 
  • Support for a wide range of Industrial Ethernet protocols including but not limited to PROFINET RT, EtherNet/IP, Modbus TCP, FL-net 
  • Several dedicated timers (9 MTUa, 4 GPTa, 2 TPUa, …), compatible to Renesas SH and RX timers 
  • Temperature range: TJ -40°C to +125°C


RZ/T1 Development Kit / Board



Renesas Electronics Europe GmbH

Further Information